- PCI Express half-length card form factor
- 8-lanes PCI Express Gen 2.0 (5Gb/s/lane)
- Xilinx Virtex-6 XC6VLX130T-2FF1156 (larger
and faster FPGAs optional)
- SNAP12 optical transmitters up to 3.3Gb/s per
channel, 850nm, (5.0 Gb/s optional)
- SNAP12 optical receivers up to 3.3Gb/s per
channel, 850nm, (5.0 Gb/s optional)
- 8GB DDR3 SDRAM arranged as
512Mx128bits @ 312.5 Mhz
- Xilinx eFUSE or battery-backed 256-bit AES
bitstream encryption
- External display connector
- RS-232 interface
- 6-signal GPIO connector configurable as 6
single ended or 3 LVDS
- 2 SMA connectors
- 20 green and 8 red user programmable LEDs
- 16 MB Flash
- 32 kB EEPROM
- Power and FPGA configuration status LEDs
- Auxiliary power connector
- JTAG interface for programming Flash and
debug
- Use as development platform or integrate into
a larger product
APPLICATIONS
- Optical Communications
- Data Capture
- Interface to data recorder/player
- Stream-thru Data Processing
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The Conduant SNAP12 Optical FPGA input/output board provides
the user with a hardware platform that is able to sustain full-duplex
high-bandwidth transfers through its 8-lane Gen2 PCI Express
interface and its 12-lane optical interface. Each PCIe lane provides
up to 5Gb/s per direction (simultaneous in and out) and each
optical channel provides up to 3.3Gb/s per direction (simultaneous
in and out). In addition, the board provides 8GB of high-speed
DDR3 SDRAM. At the center of the design is a Xilinx Virtex-6
XC6VLX130T-2FF1156 FPGA which interconnects these ports and
devices while supplying the additional resources that are available
within the FPGA.
Each lane of each optical device (transmitter or receiver) operates
independently. Thus, the optics can be configured as needed by
the user. The optical protocol (i.e. Serial FPDP, Serial Lite II,
Aurora, etc.) is up to the user.
At power-on, the Virtex-6 FPGA is automatically loaded with the
user program from an on-board flash memory device. The design
supports two different Xilinx methods of loading the FPGA, Slave
SelectMap or BPI (Byte Peripheral Interface). When loading using
the BPI protocol, AES-256 bitstream encryption is supported. The
encryption key can either be permanently programmed in a non-volatile manner into the FPGA (eFUSE) or can be preserved in a
volatile manner so long as the on-board battery is not
removed. This feature makes this product particularly attractive for
applications where protecting the FPGA intellectual property from
cloning or reverse engineering is important.
For users who need more FPGA resources than are available in
the XC6VLX130T, the pinout has been chosen to support migration
to larger, pin-compatible Virtex-6 components. These versions of
the board can be provided as special order items.
Other I/O includes an RS-232 interface, a 6-signal GPIO connector,
a connector to drive an external display, red and green LEDs, an
EEPROM, and a JTAG connector to the Virtex-6.
There are several dedicated LEDs that are used to help in
identifying power problems if they occur. In addition, the internal
operations of the FPGA can be traced through the JTAG connector
using Xilinx Chipscope Pro.
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